This invention relates to semiconductor devices utilizing copper metallization, particularly to Chemical Mechanical Planarization (CMP) of copper interconnect lines, and to preventing seam defects in narrow, isolated metal lines.
The manufacturing of semiconductor devices often includes layers of electrical circuits and/or dielectric on top of a semiconductor substrate. The electrical circuits often include narrow, isolated conductive interconnect lines circuits on one or more layers on the semiconductor substrate. The one or more layers of electrical lines and/or dielectric layers undergo Chemical Mechanical Polishing (CMP). The polishing polishes excess metal in a damascene process where holes are formed in a dielectric layer and copper is electroplated in and over the holes and on the top surface of the dielectric before the polishing. The polishing includes for example a wafer on a rotating head pressed against a polishing pad that is also rotating to grind down or polish the surface to present a more uniform planar surface. A more planar surface significantly aids the photolithography process. Dummy metals, with an appropriate size, shape, and density, promote uniform within-wafer, and particularly within-die, CMP planarization. Dummy metal structures are added to regions of low metal density. The dummy metal process involves forming holes of a given shape in the glass and electroplating copper into the holes. The copper electrochemical deposition (ECD) rate depends upon the feature size of the holes being plated.
Dummy metals are not connected to any electrical signal lines although they may be connected to ground. They are generally designed to fill a dielectric space where there is no interconnect metal so the polisher sees more uniform local metal density that will provide a more planar polished surface.
A severe seam defect problem has been observed at post CMP defect inspection. The problem occurs specifically in features that are narrow, isolated and electrically floating after the polishing is complete.
In accordance with one embodiment of the present invention, the shape, size, and density of the dummy metal structures are designed specifically when are used to surround narrow, isolated lines so that homogeneous metal density distribution across the area promotes uniform planarization rate, and consequently prevents seam defects.
In accordance with another embodiment of the present invention a method of preventing seam defects on narrow, isolated lines in the active region during CMP process with dummy metal structures includes providing with the narrow, isolated line dummy metal structures with features thereof of widths to have fill up rates that match the narrow, isolated line with a certain density of said dummy metal structures on the semiconductor device
In accordance with another embodiment of the present invention determining if the narrow, isolated line has a line width of 0.3 micron or less and if so providing dummy metal structures with features that have line widths of 0.6 micron or less.